Japanese Laid-Open Patent Publication Nos. 2009-200389 and 2012-191204 describe a wiring substrate that incorporates an electronic component such as a chip capacitor. One example of such a wiring substrate will now be described.
As illustrated in FIG. 23, a wiring substrate 200 has a structure obtained by sequentially stacking a wiring layer 201, an insulation layer 202, a wiring layer 203, an insulation layer 204, a wiring layer 205, an insulation layer 206, and a wiring layer 207.
The insulation layer 202 covers the upper surface and the side surfaces of the wiring layer 201 and exposes the lower surface of the wiring layer 201. The wiring layer 203 and a metal layer 208 are formed on the upper surface of the insulation layer 202. Via wirings extending through the insulation layer 202 electrically connect the wiring layer 203 to the wiring layer 201. The insulation layer 204 is on the upper surface of the insulation layer 202 and covers the wiring layer 203. Through holes VH10 extend through the insulation layer 204 in the thickness-wise direction and partially expose the upper surface of the wiring layer 203. In the same manner, an opening 204X extends through the insulation layer 204 in the thickness-wise direction and partially exposes the upper surface of the metal layer 208. The wiring layer 205 is formed on the upper surface of the insulation layer 204. The through holes VH10 are filled with via wirings that electrically connect the wiring layer 205 to the wiring layer 203. An electronic component 209 is mounted on the exposed upper surface of the metal layer 208 in the opening 204X. The opening 204X is filled with the insulation layer 206, which covers the surface of the wiring layer 205 and the surfaces of the electronic component 209. The wiring layer 207 is formed on the upper surface of the insulation layer 206. Via wirings extend through the insulation layer 206 and electrically connect the wiring layer 207 to the wiring layer 205 or the electronic component 209. The wiring substrate 200 may be manufactured as described below.
First, the wiring layer 201 is formed on a support substrate. Then, the insulation layer 202 is formed covering the wiring layer 201. The wiring layer 203 and the metal layer 208 are stacked on the insulation layer 202. Then, the insulation layer 204 is formed. The insulation layer 204 undergoes laser processing that forms the through holes VH10. The wiring layer 205 is formed on the upper surface of the insulation layer 204. The insulation layer 204 also undergoes laser processing that forms the opening 204X. The electronic component 209 is mounted on the metal layer 208 in the cavity defined by the opening 204X, which is filled with the insulation layer 206 that entirely covers the electronic component 209. Then, the wiring layer 207 is formed on the upper surface of the insulation layer 206. Finally, the support substrate is removed.
As described above, in the wiring substrate 200, the opening 204X is formed on the insulation layer 204, which is a single layer. Further, the opening 204X defines the cavity that accommodates the electronic component 209. Thus, the insulation layer 204 is set to have substantially the same thickness as the electronic component 209 incorporated in the wiring substrate 200. In this configuration, an increase in the thickness of the electronic component 209 increases the thickness of the insulation layer 204. This decreases the diameter at the bottom of each through hole VH10 that is formed through laser-processing. As a result, the connection reliability may be decreased between the wiring layers 203 and 205, which are electrically connected to each other by the via wirings in the through holes VH10.